Axiomise Accelerates Formal Verification Adoption Across the Industry
A unique offering of training, consulting, services, and custom software.
News provided byAxiomise Limited
Jan 26, 2023, 4:00 AM ET
LONDON, Jan. 26, 2023 (GLOBE NEWSWIRE) -- Axiomise, the leading provider of cutting-edge formal verification solutions, marked its fifth anniversary in 2022 with an impressive list of highlights, including training, consulting, services, and custom app development such as formalISA.
"Our growth has been phenomenal, especially in 2022," remarks Dr. Ashish Darbari, founder and CEO of Axiomise, who added that formal verification is recognized as an essential tool in the chip design verification flow.
Axiomise engaged with 20 customers, helping them with training, consulting, and services. Axiomise FV experts trained hundreds of new engineers through online, on-demand and instructor-led courses. Axiomise's FV 101 course was the industry's first on-demand video course that provides an excellent, easily accessible introduction to formal methods for hardware verification.
On all their projects, the Axiomise formal verification experts built exhaustive proofs of bug absence with 99% proof convergence and found 350+ bugs in six major formal verification engagements. Designs ranged in complexity from multi-threaded processors to 50G/100G/400G networking blocks to interconnects, bus fabric bridges, AI/ML, GPU blocks, RISC-V, and healthcare.
The Axiomise formalISA app for RISC-V processor verification was deployed to catch bugs and build proofs of bug absence in several cores, such as ibex, zeroriscy, cv3240p, and three WARP-V cores. It was deployed on the 64-bit CVA6 core verification to establish that all Instruction set architecture (ISA) instructions worked as expected.
Dr. Darbari started one of the industry's first verification podcasts - Formal Bytes. He gave multiple talks at the annual RISC-V summit in the USA. His talk at the RISC-V summit 2019 has garnered 26K views on the RISC-V YouTube channel. His webinar hosted by Cadence on automatic end-to-end formal verification of RISC-V processors has gained 18K views on the Axiomise YouTube channel.
Dr. Darbari was an invited keynote speaker at several events, such as the Intel India Technologist Day 2020 and the Cadence Theater Talk at DAC 2022. He gave talks on RISC-V formal verification in the Cadence CDNLive 2022 and Cadence Club Formal events in 2019 and 2022. He was a keynote speaker at the Synopsys VCFormal SIG India event in 2019 and gave a Synopsys tutorial on tackling formal verification complexity in DVCon USA 2019.
He was a panelist in DVCon USA 2018, discussing system coverage. In DVCon Europe 2019, Dr. Darbari highlighted the significance of automotive-specific, next-generation verification technologies. In the DVCon Europe 2022, he discussed the necessity of formal methods for 5G verification. In DAC 2022, Darbari emphasised the need for formal methods to exterminate the design bugs for good.
He was invited to be on Synopsys panels in DVCon USA 2018, SIG India Formal 2019, and SNUG USA 2022. Six webinars, through collaborations with Cadence Design Systems, Siemens EDA, and Synopsys, showcased Axiomise's expertise and abstraction-driven methodologies on complex verification tasks in conjunction with state-of-the-art formal verification tools.
As a result of its success and to meet the growing demand for formal verification experts, Axiomise is actively hiring. The Careers page on the Axiomise website has details.
Axiomise is accelerating formal verification adoption through its unique combination of training, consulting, services and specialized verification solutions for RISC-V. Axiomise was founded by Dr. Ashish Darbari, FBCS, DPhil (Oxford), who has been a formal verification practitioner for over two decades with 50 patents in formal verification and over 50 publications. Axiomise offers cutting-edge, formal verification training, consulting, and custom software solutions for RISC-V.
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